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LH28F040SUTD-Z4 1 4m (512k 8) flash memory figure 1. tsop configuration features ? 512k 8 bit configuration ? 5 v write/erase operation (5 v v pp , 3.3 v cc ) Cv cc for write/erase at as low as 2.9 v ? min. 2.7 v read capability C 190 ns maximum access time (v cc = 2.7 v) ? 2 banks enable the simultaneous read/write/erase operation ? 32 independently lockable blocks (16k) ? 100,000 erase cycles per block ? automated byte write/block erase C command user interface C status register ? system performance enhancement C erase suspend for read C two-byte write C bank erase ? data protection C hardware erase/write lockout during power transitions C software erase/write lockout ? independently lockable for write/erase on each block (lock block and protect set/reset) ? 20 a (maximum) i cc in cmos standby ? state-of-the-art 0.55 m etox? flash technology ? 40-pin, 1.2 mm 10 mm 20 mm tsop (type i) package 28f040suz4-1 top view 40-pin tsop 2 3 4 5 8 9 a 8 37 36 35 34 33 32 29 26 6 7 a 13 a 14 a 17 a 9 nc1 a 11 nc1 31 30 be 1 10 11 12 39 38 nc 13 28 dq 2 dq 1 dq 0 a 0 27 a 10 oe nc 14 15 16 17 18 19 25 22 24 a 1 a 2 a 3 nc 23 21 v pp v cc a 16 a 15 a 12 a 7 a 6 20 a 5 a 4 nc2 nc2 be 0 dq 7 dq 6 dq 5 dq 4 dq 3 gnd 40 1 we
LH28F040SUTD-Z4 4m (512k 8) flash memory 2 figure 2. LH28F040SUTD-Z4 block diagram output buffer input buffer dq 0 - dq 7 bank0 bank1 id register output multiplexer csr data comparator data queue register register i/o logic cui wsm 16kb block 0 16kb block 1 16kb block 14 16kb block 15 . . . . . . y gating/sensing y-decoder x-decoder oe be 0 we program/ erase voltage switch v pp v cc gnd address counter address queue latch input buffer a 0 - a 17 . . . be 1 28f040suz4-2
4m (512k 8) flash memory LH28F040SUTD-Z4 3 pin description symbol type name and function a 0 - a 13 input byte-select addresses: select a byte within one 16k block. these addresses are latched during data writes. a 14 - a 17 input block-select addresses: select 1 of 16k erase blocks. these addresses are latched during data writes, erase and lock-block operations. dq 0 - dq 7 input/output data input/output: inputs data and commands during cui write cycles. outputs array, buffer, identifier or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. be ? 0 , be ? 1 input bank enable inputs : activate the device's control logic, input buffers, decoders and sense amplifiers. ce ? must be low to select the device. when be ? 0 is low, bank0 is active. when be ? 1 is low, bank1 is active. both be ? 0 and be ? 1 must not be low at the same time. oe ? input output enable: gates device data through the output buffers when low. the outputs float to tri-state off when oe ? is high. we input write enable: controls access to the cui, page buffers, data queue registers and address queue latches. we is active low, and latches both address and data (command or array) on its rising edge. v pp supply erase/write power supply (5.0 v 0.5 v): for erasing memory array blocks or writing bytes into the flash array. v cc supply device power supply (3.3 v 0.3 v): do not leave any power pins floating. gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connection nc1, nc2 open pin: but nc1 (between pin1 and pin2) and also nc2 (pin19 and pin20) are connected inside package. introduction sharps LH28F040SUTD-Z4 4m flash memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and communication products. with innovative capabilities, 3.3 v low power operation and very high read/write per- formance, the lh28040su-z4 is also the ideal choice for designing embedded mass storage flash memory systems. the LH28F040SUTD-Z4 is a very high density, high- est performance non-volatile read/write solution for solid- state storage applications. its independently lockable 32 symmetrical blocked architecture (16k each) extended cycling, low power operation, very fast write and read performance and selective block locking pro- vide a highly flexible memory component suitable for high density memory cards, resident flash arrays and pcmcia-ata flash drives. the LH28F040SUTD-Z4s 5.0 v/3.3 v power supply operation enables the design of memory cards which can be read in 3.3 v system and written in 5.0 v/3.3 v systems. its x8 architecture allows the optimization of memory to processor inter- face. the flexible block locking option enables bundling of executable application software in a resident flash array or memory card. manufactured on sharps 0.55 m etox? process technology, the lh28f040sutd- z4 is the most cost-effective, high-density 3.3 v flash memory. LH28F040SUTD-Z4 divides 4m into two areas. each area can read/write/erase independently. for example, while you write and erase on one area, you can simul- taneously read the data from the other area. this enables users to reduce the number of components in their system.
LH28F040SUTD-Z4 4m (512k 8) flash memory 4 description the LH28F040SUTD-Z4 is a high performance 4m (4,194,304 bit) block erasable non-volatile random access memory organized as 256k 8 2 banks. the LH28F040SUTD-Z4 includes thirty-two 16k (16,384) blocks. a chip memory map is shown in figure 3. the two banks, the one selected by be ? 0 (bank0) and the other selected by be ? 1 (bank1) can be controlled independently. for example, while erase the data in bank0, the data in bank1 can be read out. the implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use. among the significant enhancements of the LH28F040SUTD-Z4: ? 3 v read, 5 v write/erase operation (5 v v pp , 3 v v cc ) ? low power capability (2.7 v v cc read) ? improved write/erase performance (two-byte serial write, bank erase) ? dedicated block write/erase protection ? command-controlled memory protection set/reset capability the LH28F040SUTD-Z4 will be available in a 40-pin, 1.2 mm thick 10 mm 20 mm tsop (type i) pack- age. this form factor and pinout allow for very high board layout densities. a command user interface (cui) serves as the sys- tem interface between the microprocessor or micro- controller and the internal memory operation. internal algorithm automation allows byte wr ites and block erase operations to be executed using a two- write command sequence to the cui in the same way as the lh28f008sa 8m flash memory. a superset of commands have been added to the basic lh28f008sa command-set to achieve higher write performance and provide additional capabilities. these new commands and features include: ? software locking of memory blocks ? memory protection set/reset capability ? two-byte serial writes in 8-bit systems ? bank erase all unlocked blocks writing of memory data is performed typically within 20 s. a block erase operation erases one of the 32 blocks in typically 1.5 seconds, independent of the other blocks. LH28F040SUTD-Z4 allows to erase all unlocked blocks for each bank selected by be ? 0 or be ? 1 . it is de- sirable in case of which you have to implement erase operation maximum 32 times. LH28F040SUTD-Z4 enab les tw o-byte ser ial write which is operated by three times command input. this feature can improve system write performance by up to typically 17 s per byte. all operations are started by a sequence of write commands to the device. status register (described in detail later) provide information on the progress of the requested operation. same as the lh28f008sa, LH28F040SUTD-Z4 requires an operation to complete before the next op- eration can be requested, also it allows to suspend block erase to read data from any other block, and allow to resume erase operation. the LH28F040SUTD-Z4 provides user-selectable block locking to protect code or data such as device drivers, pcmcia card information, rom-executable os or application code. each block has an associated non- volatile lock-bit which determines the lock status of the block. in addition, the LH28F040SUTD-Z4 has a soft- ware controlled master write protect circuit which pre- vents any modifications to memory blocks whose lock- bits are set. when the device power-up, write protect set/ confirm command must be written both in bank0 and bank1. otherwise, all lock bits in the device remain being locked, cant perform the wr ite to each block and single block erase. write protect set/confirm command must be written to reflect the actual lock status. how- ever, when the device power-on, erase all unlocked blocks can be used. if used, erase is performed with reflecting actual lock status, and after that write and block erase can be used. the LH28F040SUTD-Z4 contains status register to accomplish various functions: ? a compatible status register (csr) which is 100% compatible with the lh28f008sa flash memorys status register. this register, when used alone, provides a straightforward upgrade capabil- ity to the LH28F040SUTD-Z4 from a lh28f008sa based design. the LH28F040SUTD-Z4 is specified for a maximum access time of 150 ns (t acc ) at 3.3 v operation (3.0 to 3.6 v) over the commercial temper ature range (-20 to +70c). a corresponding maximum access time of 190 ns (t acc ) at 2.7 v (-20 to +70c) is achieved for reduced power consumption applications.
4m (512k 8) flash memory LH28F040SUTD-Z4 5 figure 3. memory map memory map the LH28F040SUTD-Z4 incorporates an automatic power saving (aps) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching). in aps mode, the typical i cc current is 2 ma at 3.3 v. a bank reset mode of operation is enabled when whole be ? 0 (or be ? 1 ), we ? and oe ? hold low more than 5 s. in this mode, all operations are aborted, the internal control circuit is reset and csr register is cleared. when the device power up, this bank reset operation must be executed for each bank to initialize the control circuit. if be ? x (either be ? 0 or be ? 1 which is in low state) and or we ? and or oe ? and or goes high, chip reset mode will be finished. it needs more than 750 ns from one of the be ? x , we ? or oe ? goes high until output data are valid. it is impossible to reset the whole chip at once, the bank reset must be executed separately for bank0 and bank1. a cmos standby mode of operation is enabled when be ? x transitions high with all input control pins at cmos levels. in this mode, the device draws an i cc standby current of 20 a. please do not execute reprogramming 0 for the bit which has already been programmed 0. overwrite op- eration may generate unerasable bit. in case of repro- gramming 0 to the data which has been programmed 1. ? program 0 for the bit in which you want to change data from 1 to 0. ? program 1 for the bit which has already been pro- grammed 0. for example, changing data from 10111101 to 10111100 requires 11111110 programming. 15 3ffffh bank0 (be 0 = low) bank1 (be 1 = low) 3c000h 3bfffh 38000h 37fffh 34000h 33fffh 30000h 2ffffh 2c000h 2bfffh 28000h 27fffh 24000h 23fffh 20000h 1ffffh 1c000h 1bfffh 18000h 17fffh 14000h 13fffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 00000h 14 13 12 11 10 9 8 7 6 5 4 3 2 0 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 1 16kb block 16kb block 15 3ffffh 3c000h 3bfffh 38000h 37fffh 34000h 33fffh 30000h 2ffffh 2c000h 2bfffh 28000h 27fffh 24000h 23fffh 20000h 1ffffh 1c000h 1bfffh 18000h 17fffh 14000h 13fffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 00000h 14 13 12 11 10 9 8 7 6 5 4 3 2 0 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 1 16kb block 16kb block 28f040suz4-3
LH28F040SUTD-Z4 4m (512k 8) flash memory 6 bus operations, commands and status register definitions bus operations mode be ? 0 be ? 1 oe ? we a 0 dq 0 - dq 7 note read bank 0 v i l v i h v il v ih xd out 1 bank 1 v i h v il output disable x x v ih v ih xhigh-z 1 standby v ih v ih xxxhigh-z 1 manufacturer id bank 0 v i l v i h v il v ih v il b0h 2 bank 1 v ih v il device id bank 0 v i l v i h v il v ih v ih 31h 2 bank 1 v ih v il write bank 0 v i l v i h v ih v il xd in 1, 3 bank1 v ih v il notes: 1. x can be v ih or v il for address or control pins, which is either v ol or v oh . 2. a 0 at v il provide manufacturer id codes. a 0 at v ih provide device id codes. all other addresses are set to zero. 3. commands for different erase operations, d ata wr ite operations, and lock-block operations can only be successfully completed when v pp = v pph . 4. both be ? 0 and be ? 1 must not be low at the same time.
4m (512k 8) flash memory LH28F040SUTD-Z4 7 command first bus cycle second bus cycle note oper. address data oper. address data read array write x ffh read aa ad intelligent identifier write x 90h read ia id 1 read compatible status register write x 70h read x csrd 2 clear status register write x 50h 3 byte write write x 40h write wa wd alternate byte write write x 10h write wa wd block erase/confirm write x 20h write ba d0h 4 erase suspend/resume write x b0h write x d0h 4 lh28f008sa-compatible mode command bus definitions following is the commands to be applied to each bank. address data aa = array address ad = array data ba = block address csrd = csr data ia = identifier address id = identifier data wa = write address wd = write data x = dont care notes: 1. following the intelligent identifier command, two read operations access the manufacturer and device signature codes. 2. the csr is automatically available after device enters data write, erase or suspend operations. 3. clears csr.3, csr.4, and csr.5. see status register definitions. 4. while device performs block erase, if you issue erase suspend command (b0h), be sure to confirm ess (erase-suspend-status) is set to 1 on compatible status register. in the case, ess bit was not set to 1, also completed the erase (ess = 0, wsms = 1), be sure to issue resume command (d0h) after completed next erase command. beside, when the erase suspend command is issued, while the device is not in erase, be sure to issue resume command (d0h) after the next erase complete.
LH28F040SUTD-Z4 4m (512k 8) flash memory 8 command first bus cycle second bus cycle third bus cycle note oper. add. data oper. add. data oper. add. data protect set/confirm write x 57h write 0ffh d0h 1, 2, 6 protect reset/confirm write x 47h write 0ffh d0h 3, 6 lock block/confirm write x 77h write ba d0h 1, 2, 4 bank erase all unlocked blocks write x a7h write x d0h 1, 2 two-byte write write x fbh write a10 wd (l, h) write wa wd (h, l) 1, 2, 5 LH28F040SUTD-Z4 performance enhancement command bus definitions following is the commands to be applied to each bank. address data ba = block address ad = array data wa = write address wd (l, h) = write data (low, high) x = dont care wd (h, l) = write data (high, low) notes: 1. after initial device power-up, or reset is completed, the block lock status bit default to the locked state independent of the data in the corresponding lock bits. in order to upload the lock bit status, it requires to write protect set/confirm command. 2. to reflect the actual lock-bit status, the protect set/confirm command must be written after lock block/confirm command. 3. when protect reset/confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits. 4. the lock block/confirm command must be written after protect reset/confirm command was written. 5. a 0 is automatically complemented to load second byte of data a 0 value determines which wd is supplied first: a 0 = 0 looks at the wdl, a 0 = 1 looks at the wdh. 6. second bus cycle address of protect set/confirm and protect reset/confirm command is 0ffh. specifically a 9 - a 8 = 0, a 7 - a 0 = 1, others are dont care. wsms ess es dws vpps r r r 76543210 compatible status register following is the commands to be applied to each bank. csr.7 = write state machine status (wsms) 1 = ready 2 = busy csr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase csr.4 = data-write status (dws) 1 = error in data write 0 = data write successful csr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok notes: 1. ry ? /by ? output or wsms bit must be checked to determine completion of an operation (erase suspend, erase or data write) before the appropriate status bit (ess, es or dws) is checked for success. 2. if dws and es are set to 1 during an erase attempt, an improper command sequence was entered. clear the csr and attempt the operation again. 3. the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp s level only after the data-write or erase command sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v ppl and v pph . 4. csr.2 - csr.0 = reserved for further enhancements. these bits are reserved for future use and should be masked out when polling the csr.
4m (512k 8) flash memory LH28F040SUTD-Z4 9 4m dual work flash memory software algorithms overview with the advanced command user interface, its per- formance enhancement commands and status regis- ters, the software code required to perform a given operation may become more intensive but it will result in much higher write/erase performance compared with current flash memory architectures. the software flowcharts describing how a given operation proceeds are shown here. figures 4 through 6 depict flowcharts using the 2nd generation flash device in the lh28f008sa-compatible mode. figures 7 through 12 depict flowcharts using the 2nd genera- tion flash devices performance enhancement com- mands mode. when the device power-up or reset is completed, set write protect command must be written to both the bank selected by be ? 0 and be ? 1 in order to reflect actual block lock status. when the device power-up or reset is completed, all blocks come up locked. therefore, byte write, two byte serial wr ite and block erase can not be performed in each block. however, at that time, erase all unlocked block is performed normally, if used, and reflect actual lock status, also the unlocked block data is erased. when the device power-up or reset is completed, set write protect command must be written to reflect actual block lock status. reset wr ite protect command must be written be- fore wr ite block lock command. to reflect actual block lock status, set write protect command is succeeded. the compatible status register (csr) used to determine which blocks are locked. in order to see lock status of certain block, a byte write command (wa = block address, wd = fhh) is written to the cui, after issuing set write protect command. if csr.7, csr.5 and csr.4 (wsms, es and dws) are set to 1s, the block is locked. if csr.7 is set to 1, the block is not locked. reset write protect command enables write/erase operation to each block. in the case of block erase is performed, the block lock information is also erased. block lock command and set write protect command must be written to pro- hibit write/erase operation to each block. there are unassigned commands. it is not recom- mended that the customer use any command other than the valid commands specified in command bus defi- nitions. sharp reserved the right to redefine these codes for future functions.
LH28F040SUTD-Z4 4m (512k 8) flash memory 10 figure 4. byte writes with compatible status register start bus operation command comments write 40h or 10h write data/address csr.7 = 0 1 0 1 0 1 csr full status check if desired operation complete clear csrd retry/error recovery data write successful v pp low detect read csrd (see above) csr.4, 5 = csr.3 = write write read standby byte write d = 40h or 10h a = x d = wd a = wa q = csrd toggle be 0 , be 1 or oe to update csrd. a = x repeat for subsequent byte writes. csr full status check can be done after each byte write, or after a sequence of byte writes. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. check csr.7 1 = wsm ready 0 = wsm busy bus operation command csr full status check procedure comments standby standby check csr.4, 5 1 = data write unsuccessful 0 = data write successful check csr.3 1 = v pp low detect 0 = v pp ok csr.3, 4, 5 should be cleared, if set, before further attempts are initiated. 28f040suz4-4 read compatible status register
4m (512k 8) flash memory LH28F040SUTD-Z4 11 figure 5. block erase with compatible status register start bus operation command comments write 20h write d0h and block address csr.7 = 0 no yes 1 0 1 0 1 csr full status check if desired operation complete clear csrd retry/error recovery (note) erase successful v pp low detect read csrd (see above) suspend erase suspend erase loop csr.4, 5 = csr.3 = write write read standby block erase confirm d = 20h a = x d = d0h a = ba q = csrd toggle be 0 , be 1 or oe to update csrd. a = x repeat for subsequent block erasures. csr full status check can be done after each block erase, or after a sequence of block erasures. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. check csr.7 1 = wsm ready 0 = wsm busy bus operation command csr full status check procedure comments standby standby check csr.4, 5 1 = erase error 0 = erase successful both 1 = command sequence error csr.3, 4, 5 should be cleared, if set, before further attempts are initiated. note: if csr.3 (vpps) is set to '1', after clearing csr.3/4/5, 1. issue reset wp command. 2. retry single block erase command. 3. set wp command is issued, if necessary. if csr.3 (vpps) is set to '0', after clearing csr.3/4/5, 1. retry single block erase command. where power off or chip reset during erase operation, 1. clear csr.3/4/5 and issue reset wp command, 2. retry single block erase command. 3. set wp command is issued, if necessary. 28f040suz4-5 read compatible status register check csr.3 1 = v pp low detect 0 = v pp ok
LH28F040SUTD-Z4 4m (512k 8) flash memory 12 figure 6. erase suspend to read array with compatible status register start bus operation command comments write b0h csr.7 = 0 1 0 1 read array data erase resumed erase completed write read standby erase suspend d = b0h a = x q = csrd toggle be 0 , be 1 or oe to update csrd. a = x see command bus cycle notes for description of codes. check csr.7 1 = wsm ready 0 = wsm busy standby check csr.6 1 = erase suspended 0 = erase completed write read array d = ffh a = x write erase resume d = d0h a = x read q = ad read must be from block other than the one suspended. 28f040suz4-6 write ffh write d0h read compatible status register csr.6 = done reading read array data write ffh no yes
4m (512k 8) flash memory LH28F040SUTD-Z4 13 figure 7. block locking scheme start bus operation command comments csr.7 = 0 1 operation complete read read read write reset write protect q = csrd toggle be 0 , be 1 or oe to update csrd. 1 = wsm ready 0 = wsm busy d = d0h a = ba q = csrd toggle be 0 , be 1 or oe to update csrd. 1 = wsm ready 0 = wsm busy q = csrd toggle be 0 , be 1 , or oe to update csrd. 1 = wsm ready 0 = wsm busy note: see csr full status check for data-write operation. if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. write ffh after the last operation to reset device to read array mode. see command bus definitions for description of codes. after write d = 47h a = x, write d = d0h a = 0ffh write lock block confirm set write protect d = 77h a = x after write d = 57h a = x, write d = d0h a = 0ffh write write 28f040suz4-7 read compatible status register reset wp read compatible status register write d0h and block address read compatible status register csr.7 = csr.7 = csr.4, 5 = 0 1 1 0 1 0 lock another block no yes (note) write 77h set wp
LH28F040SUTD-Z4 4m (512k 8) flash memory 14 figure 8. updating data in a locked block start operation complete operation complete flow to add data notes: 1. use reset-write-protect flowchart. enable write/erase operation to all blocks. 2. use block-erase flowchart. erasing a block clears any previously established lockout for that block. 3. use set-write-protect flowchart. this step re-implements protection to locked blocks. 4. use byte-write or 2-byte-write flowchart sequences to write data. 5. use block-lock flowchart to write lock bit if desired. flow to rewrite data 28f040suz4-8 reset wp (note 1) erase block (note 2) set wp (note 3) start reset wp (note 1) write more data to block (note 4) set wp (note 3) write new data to block (note 4) relock block (note 5)
4m (512k 8) flash memory LH28F040SUTD-Z4 15 figure 9. two-byte serial writes with compatible status registers start bus operation command comments csr.7 = 0 1 operation complete read write write 2-byte write q = csrd toggle be 0 , be 1 or oe to update csrd. 1 = wsm ready 0 = wsm busy q = csrd toggle be 0 , be 1 or oe to update csrd. 1 = wsm ready 0 = wsm busy d = wd a 0 = 0 loads low byte of data register. a 0 = 1 loads high byte of data register. other addresses = x note: if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. csr full status check can be done after each 2-byte write, or after a sequence of 2-byte writes. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. d = fbh a = x write d = wd a = wa internally, a 0 is automatically complemented to load the alternate byte location of the data register. read 28f040suz4-9 read compatible status register write fbh write data/a 0 csr.7 = csr.4, 5 = 1 0 1 0 another 2-byte write no yes (note) write data/address read compatible status register
LH28F040SUTD-Z4 4m (512k 8) flash memory 16 figure 10. bank erase all unlocked blocks with compatible status registers start (note) bus operation command comments write a7h csr.7 = 0 yes no 1 0 1 0 1 csr full status check if desired operation complete write d0h clear csrd retry/error recovery (note) erase successful v pp low detect read csrd (see above) suspend erase suspend erase loop csr.4, 5 = csr.3 = write write read standby erase all unlocked blocks confirm d = a7h a = x d = d0h a = x q = csrd toggle be 0 , be 1 or oe to update csrd. a = x csr full status check can be done after erase all unlocked block, or after a sequence of erasures. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. note: where power off or reset during erase operation, 1. clear csr.3/4/5 and issue reset wp command, 2. retry erase all unlocked block erase command to erase all blocks, or issue single block erase to erase all of the unlocked blocks in sequence. 3. set wp command is issued, if necessary. check csr.7 1 = wsm ready 0 = wsm busy bus operation command csr full status check procedure comments standby standby check csr.4, 5 1 = erase error 0 = erase successful both 1 = command sequence error csr.3, 4, 5 should be cleared, if set, before further attempts are initiated. note: if csr.3 (vpps) is set to '1', after clearing csr.3/4/5, 1. issue reset wp command, 2. retry erase all unlocked block erase command to erase all blocks, or issue single block erase to erase all of the unlocked blocks in sequence. 3. set wp command is issued, if necessary. if csr.3 (vpps) is set to '0', after clearing csr.3/4/5, 1. retry erase all unlocked block erase command. 28f040suz4-10 read compatible status register check csr.3 1 = v pp low detect 0 = v pp ok
4m (512k 8) flash memory LH28F040SUTD-Z4 17 figure 11. set write protect start csr.7 = 0 1 write 57h write confirm data/address read compatible status register csr.7 = 0 0 1 1 (note) csr.4, 5 = 28f040suz4-11 read compatible status register operation complete bus operation command comments read write write set write protect set confirm check csr.7 1 = wsm ready 0 = wsm busy d = d0h a = 0ffh (a 9 - a 8 = 0, a 7 - a 0 = 1, others = x) note: if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. upon device power-up or reset is complete, set write protect command must be written to reflect the actual lock-bit status. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. d = 57h a = x read check csr.7 1 = wsm ready 0 = wsm busy read check csr.4, 5 1 = unsuccesful 0 = successful
LH28F040SUTD-Z4 4m (512k 8) flash memory 18 figure 12. reset write protect start csr.7 = 0 1 write 47h write confirm data/address read compatible status register csr.7 = 0 0 1 1 (note) csr.4, 5 = 28f040suz4-12 read compatible status register operation complete bus operation command comments read write write reset write protect reset confirm check csr.7 1 = wsm ready 0 = wsm busy d = d0h a = 0ffh (a 9 - a 8 = 0, a 7 - a 0 = 1, others = x) note: if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. reset write protect command enables write/erase operation to all blocks. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. d = 47h a = x read check csr.7 1 = wsm ready 0 = wsm busy read check csr.4, 5 1 = unsuccesful 0 = successful
4m (512k 8) flash memory LH28F040SUTD-Z4 19 * warning: stressing the device bey ond the abso- lute maximum ratings may cause permanent dam- age. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the oper ating conditions may affect device reliability. electrical specifications absolute maximum ratings* temperature under bias ...................... -20c to +80c storage temperature ......................... -65c to +125c symbol parameter min. max. units test conditions note t a operating temperature, commercial 0 70.0 c ambient temperature 1 v cc v cc with respect to gnd -0.2 7.0 v 2 v pp v pp supply voltage with respect to gnd -0.2 7.0 v 2 v voltage on any pin (except v cc , v pp ) with respect to gnd -0.5 v cc + 0.5 v 2 i current into any non-supply pin 30 ma i out output short circuit current 100.0 ma 3 notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is -0.5 v on input/output pins. during transitions, this level may undershoot to -2.0 v for periods < 20 ns. maximum dc voltage on input/output pins is v cc + 0.5 v which, during transitions, may overshoot to v cc + 2.0 v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. capacitance note: 1. sampled, not 100% tested. 2. be ? 0 and be ? 1 have half the value of this. symbol parameter typ. max. units test conditions note c in capacitance looking into an address/control pin 14 20 pf t a = 25c, f = 1.0 mhz 1, 2 c out capacitance looking into an output pin 18 24 pf t a = 25c, f = 1.0 mhz 1 c load load capacitance driven by outputs for timing specifications 50 pf for v cc = 3.3 v 0.3 v 1 equivalent testing load circuit v cc 10% 2.5 ns 50 w transmission line delay
LH28F040SUTD-Z4 4m (512k 8) flash memory 20 timing nomenclature for 3.3 v systems use 1.5 v cross point definitions. each timing parameter consists of 5 characters. some common examples are defined below: t ce t elqv time (t) from be ? (e) going low (l) to the outputs (q) becoming valid (v) t oe t glqv time (t) from oe ? (g) going low (l) to the outputs (q) becoming valid (v) t acc t avqv time (t) from address (a) valid (v) to the outputs (q) becoming valid (v) t as t avwh time (t) from address (a) valid (v) to we ? (w) going high (h) t dh t whdx time (t) from we ? (w) going high (h) to when the data (d) can become undefined (x) figure 13. transient input/output reference waveform (v cc = 3.3 v) figure 14. transient equivalent testing load circuit (v cc = 3.3 v) pin characters pin states a address inputs h high d data inputs l low q data outputs v valid ebe ? (byte enable) 1 x driven, but not necessarily valid goe ? (output enable) z high impedance w we (write enable) v any voltage level 3 v v cc at 3.0 v min. note: 1. be ? x means either be ? 0 or be ? 1 . input test points output 3.0 0.0 1.5 1.5 28f040suz4-13 note: ac test inputs are driven at 3.0 v for a logic '1' and 0.0 v for a logic '0'. input timing begins and output timing ends at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. 2.5 ns of 50 w transmission line total capacitance = 50 pf from output under test test point 28f040suz4-14
4m (512k 8) flash memory LH28F040SUTD-Z4 21 dc characteristics v cc = 3.3 v 0.3 v, t a = -20c to +70c following is the current consumption of one bank. for the current consumption of one device total, please refer to note 5. symbol parameter typ. min. max. units test conditions note i il input load current 2 a v cc = v cc max., v in = v cc or gnd 1 i lo output leakage current 20 a v cc = v cc max., v in = v cc or gnd 1 i ccs v cc standby current 510a v cc = v cc max., be ? 0 , be ? 1 = v cc 0.2 v 1, 4, 5 0.3 4 ma v cc = v cc max., be ? 0 , be ? 1 = v ih i ccr 1 v cc read current (10 mhz operation) 35 ma v cc = v cc max., cmos: be ? 0 , be ? 1 = gnd 0.2 v inputs = gnd 0.2 v or v cc 0.2 v, ttl: be ? 0 , be ? 1 = v il, inputs = v il or v ih , f = 10 mhz, i out = 0 ma 1, 3, 4, 5 i ccr 2 v cc read current (5 mhz operation) 10 20 ma v cc = v cc max., cmos: be ? 0 , be ? 1 = gnd 0.2 v inputs = gnd 0.2 v or v cc 0.2 v, ttl: be ? 0 , be ? 1 = v il, inputs = v il or v ih , f = 5 mhz, i out = 0 ma 1, 3, 4, 5 i ccw v cc write current 8 12 ma byte/two-byte serial write in progress 1, 5 i cce v cc block erase current 6 12 ma block erase in progress 1, 5 i cces v cc erase suspend current 36ma be ? 0 , be ? 1 = v ih block erase suspended 1, 2, 5 i pps v pp standby current 1 10 a v pp v cc 1, 5
LH28F040SUTD-Z4 4m (512k 8) flash memory 22 dc characteristics (continued) v cc = 3.3 v 0.3 v, t a = -20c to +70c notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 3.3 v, v pp = 5.0 v, t = 25c. 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. automatic power saving (aps) reduces i ccr to less than 2 ma in static operation. 4. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 5. these are the values of the current which is consumed within one bank area. the value for the bank0 and bank1 should be added in order to calculate the value for the whole chip. if the bank0 is in write state and bank1 is in read state, the i cc = i ccw + i ccr . if both banks are in standby mode, the value for the device is 2 times the value in the above table. symbol parameter type min. max. units test conditions note i ppr v pp read current 65 200 a v pp > v cc 1, 5 i ppw v pp write current 15 35 ma v pp = v pph , byte/two-byte serial write in progress 1, 5 i ppe v pp erase current 20 40 ma v pp = v pph , block erase in progress 1, 5 i ppes v pp erase suspend current 65 200 a v pp = v pph , block erase suspended 1, 5 v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v cc + 0.3 v v ol output low voltage 0.4 v v cc = v cc min. and i ol = 4 ma v oh 1 output high voltage 2.4 v i oh = -2 ma v cc = v cc min. v oh 2 v cc - 0.2 v i oh = 100 a v cc = v cc min. v ppl v pp during normal operations 0.0 5.5 v v pph v pp during write/erase operations 5.0 4.5 5.5 v v lko v cc erase/write lock voltage 1.4 v
4m (512k 8) flash memory LH28F040SUTD-Z4 23 ac characteristics - read only operations 1 v cc = 3.3 v 0.3 v, t a = -20c to +70c symbol parameter min. max. units note t avav read cycle time 150 ns t avgl address setup to oe ? going low 0 ns 3 t avqv address to output delay 150 ns t elqv be ? 0 , be ? 1 to output delay 150 ns 2 t glqv oe ? to output delay 50 ns 2 t elqx be ? 0 , be ? 1 to output in low z 0 ns 3 t ehqz be ? 0 , be ? 1 to output in high z 55 ns 3 t glqx oe ? to output in low z 0 ns 3 t ghqz oe ? to output in high z 40 ns 3 t oh output hold from address, be ? 0 , be ? 1 or oe ? change, whichever occurs first 0ns3 ac characteristics - read only operations 1 (continuted) v cc = 2.85 v 0.15 v, t a = -20c to +70c symbol parameter min. max. units note t avav read cycle time 190 ns t avgl address setup to oe ? going low 0 ns 3 t avqv address to output delay 190 ns t elqv be ? 0 , be ? 1 to output delay 190 ns 2 t glqv oe ? to output delay 65 ns 2 t elqx be ? 0 , be ? 1 to output in low z 0 ns 3 t ehqz be ? 0 , be ? 1 to output in high z 70 ns 3 t glqx oe ? to output in low z 0 ns 3 t ghqz oe ? to output in high z 55 ns 3 t oh output hold from address, be ? 0 , be ? 1 or oe ? change, whichever occurs first 0ns3 notes: 1. see ac input/output reference waveforms for timing measurements, figure 4. 2. oe ? may be delayed up to t elqv - t glqv after the falling edge of be ? 0 , be ? 1 without impact on t elqv . 3. sampled, not 100% tested.
LH28F040SUTD-Z4 4m (512k 8) flash memory 24 figure 15. read timing waveforms 28f040suz4-15 t avav addresses stable v cc power-up standby device and address selection outputs enabled data valid standby v cc power-down addresses (a) v ih v il be x (e) (note) v ih v il t avgl t glqv t elqv t glqx t elqx t avqv t ehqz t ghqz t oh oe (g) v ih v il we (w) v ih v il data (d/q) v oh v ol v cc 3.3 v gnd high-z note: be x means either be 0 or be 1 high-z valid output . . . . . . . . . . . . . . . . . . . . .
4m (512k 8) flash memory LH28F040SUTD-Z4 25 power-up and reset timings figure 16. v cc power-up and rp ? reset waveforms 28f040suz4-16 t phqv t wlpl t glrs t elrs t ehrs t ghrs valid valid 3.3 v outputs 3.3 v 3.0 v t avqv 0 v 3.3 v be x (e) (note) oe (g) we (w) address (a) data (q) v cc (3.5 v) v cc power up note: be x means either be 0 or be 1 symbol parameter min. max. units note t wlpl we low to v cc at 3.0 v min. 5 s 1 t avqv address valid to data valid for v cc = 3.3 v 0.3 v 150 ns 2 t phqv we high to data valid for v cc = 3.3 v 0.3 v 500 ns 2 t elrs be ? 0 and be ? 1 setup to we going low 100 ns t glrs oe ? setup to we going low 100 ns t ehrs be ? 0 and be ? 1 hold from we going high 100 ns t ghrs oe ? hold from we going high 100 ns notes: be ? 0 , be ? 1 and oe ? must be set high once after power-up. be ? 0 and be ? 1 must not be set low at the same time. 1. chip reset is enabled when the low state of all be ? 0 (or be ? 1 ), oe ? and we ? exceeds 5 s. especially when you will power on the chip, execute an above chip reset sequence for a protection from noise. all be ? 0 (or be ? 1 ), oe ? and we ? must not be low, except for the purpose of chip reset. 2. these values are shown for 3.3 v v cc operation. refer to the ac characteristics read only operations also.
LH28F040SUTD-Z4 4m (512k 8) flash memory 26 ac characteristics for we ? - controlled command write operations 1 v cc = 3.25 v 0.35 v, t a = -20c to +70c notes: 1. read timing during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. write/erase durations are measured to valid status register (csr) data. 5. byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of we ? for all command write operations. 7. the maximum value of byte write time is the maximum write time inside the chip. it is not the time until the whole writing procedure is completed properly. it is necessary to check csr to see if the writing procedure is properly completed. symbol parameter typ. min. max. units note t avav write cycle time 150 ns t vpwh v pp set up to we going high 100 ns 3 t elwl be ? 0 and be ? 1 setup to we going low 0 ns t avwh address setup to we going high 110 ns 2, 6 t dvwh data setup to we going high 110 ns 2, 6 t wlwh we pulse width 110 ns t whdx data hold from we high 10 ns 2 t whax address hold from we high 10 ns 2 t wheh be ? 0 and be ? 1 hold from we high 10 ns t whwl we pulse width high 75 ns t ghwl read recovery before write 0 ns t whgl write recovery before read 120 ns t qvvl v pp hold from valid status register data 0 s t whqv 1 duration of byte write operation 20 8 250 s 4, 5, 7 t whqv 2 duration of block erase operation 0.3 s 4
4m (512k 8) flash memory LH28F040SUTD-Z4 27 figure 17. waveforms for command write operations addresses (a) (note 1) v ih v il a in d in d in d in d in d out be x (e) (note 3) v ih v il oe (g) v ih v il we (w) v ih v il data (d/q) v ih v il t avav t whgl t whwl t wlwh t dvwh t qvvl t avwh t whax t elwl t wheh t whqv 1, 2 t ghwl t whdx t vpwh 28f040suz4-17 (note 2) high-z write data-write or erase setup command write valid address and data (data-write) or erase confirm command automated data-write or erase delay notes: 1. this address string depicts data-write/erase cycles with corresponding verification via csrd. 2. this cycle is invalid when using csrd for verification during data-write/erase operations. 3. be x means either be 0 or be 1 v pp (v) v pph v ppl read compatible status register data
LH28F040SUTD-Z4 4m (512k 8) flash memory 28 ac characteristics for be ? - controlled command write operations 2 v cc = 3.25 v 0.35 v, t a = -20c to +70c notes: 1. read timing during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. write/erase durations are measured to valid status register (csr) data. 5. byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of be ? 0 or be ? 1 for all command write operations. 7. the max. value of byte write time is the maximum wrtie time inside the chip. it is not the time until the whole writing procedure is completed properly. it is necessary to check csr to see if the writing procedure is properly completed. symbol parameter typ. min. max. units note t avav write cycle time 150 ns t vpeh v pp set up to be ? 0 or be ? 1 going high 100 ns 3 t wlel we setup to be ? 0 or be ? 1 going low 0 ns t aveh address setup to be ? 0 or be ? 1 going high 110 ns 2, 6 t dveh data setup to be ? 0 or be ? 1 going high 110 ns 2, 6 t eleh be ? 0 or be ? 1 pulse width 110 ns t ehdx data hold from be ? 0 or be ? 1 high 10 ns 2 t ehax address hold from be ? 0 or be ? 1 high 10 ns 2 t ehwh we hold from be ? 0 or be ? 1 high 10 ns t ehel be ? 0 or be ? 1 pulse width high 75 ns t ghel read recovery before write 0 ns t ehgl write recovery before read 120 ns t qvvl v pp hold from valid status register data 0 s t ehqv 1 duration of byte write operation 20 8 250 s 4, 5, 7 t ehqv 2 duration of block erase operation 0.3 s 4
4m (512k 8) flash memory LH28F040SUTD-Z4 29 figure 18. alternate ac waveforms for command write operations addresses (a) (note 1) v ih v il a in d in d in d in d in d out we (w) v ih v il oe (e) v ih v il be x (e) (note 3) v ih v il data (d/q) v ih v il t avav t ehgl t ehel t eleh t dveh t qvvl t aveh t ehax t wlel t ehwh t ehqv 1, 2 t ghel t ehdx t vpeh 28f040suz4-18 (note 2) high-z write data-write or erase setup command write valid address and data (data-write) or erase confirm command automated data-write or erase delay notes: 1. this address string depicts data-write/erase cycles with corresponding verification via csrd. 2. this cycle is invalid when using csrd for verification during data-write/erase operations. 3. be x means either be 0 or be 1 v pp (v) v pph v ppl read compatible status register data
LH28F040SUTD-Z4 4m (512k 8) flash memory 30 erase and byte write performance v cc = 3.25 v 0.35 v, t a = -20c to +70c notes: 1. 25c, v pp = 5.0 v 2. excludes system-level overhead. it actually indicates the time from input write/erase command until bit7 of status register becomes ready (wsms = 0). 3. the max. value of byte write time is the maximum write time inside the chip. it is not the time until the whole writing procedure is com- pleted properly. it is necessary to check csr to see if the writing procedure is properly completed. 4. depends on the number of protected blocks. symbol parameter typ. (1) min. max. units test conditions note t whrh 1 byte write time 20 250 s 2, 3 t whrh 2 two-byte serial write time 34 s 2 t whrh 3 16kb block write time 0.33 1.0 s byte write mode 2 t whrh 4 16kb block write time 0.28 1.0 s two-byte serial write mode 2 block erase time (16kb) 0.8 10 s 2 2m bit bank erase time 9 - 15 s 2, 4
4m (512k 8) flash memory LH28F040SUTD-Z4 31 ordering information dimensions in mm [inches] maximum limit minimum limit 40tsop (tsop040-p-1020) 40tsop detail see detail 1.19 [0.047] max. 0 - 10? 0.22 [0.009] 0.02 [0.001] 1.10 [0.043] 0.90 [0.035] 0.49 [0.019] 0.39 [0.015] 0.49 [0.019] 0.39 [0.015] 0.125 [0.005] 10.20 [0.402] 9.80 [0.386] 0.50 [0.020] typ. 0.25 [0.010] 0.15 [0.006] 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776] 0.18 [0.007] 0.08 [0.003] 1 20 21 40 40-pin, 1.2 mm x 10 mm x 20 mm tsop (type i) (tsop040-p-1020) lh28f040su device type t package 28f040suz4-19 example: lh28f040sut-z4 (4m (512k x 8) flash memory, 190 ns, 40-pin tsop) 4m (512k x 8) flash memory -z4 speed 190 access time (ns) dual works d
sharp reserves the right to make changes in specifications at any time and without notice. sharp does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. north america europe asia sharp electronics corporation microelectronics group 5700 nw pacific rim blvd., m/s 20 camas, wa 98607, u.s.a. phone: (360) 834-2500 telex: 49608472 (sharpcam) facsimile: (360) 834-8903 http://www.sharpmeg.com sharp electronics (europe) gmbh microelectronics division sonninstra? 3 20097 hamburg, germany phone: (49) 40 2376-2286 telex: 2161867 (heeg d) facsimile: (49) 40 2376-2232 life support policy sharp components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the sharp corporation. sharp corporation integrated circuits group 2613-1 ichinomoto-cho tenri-city, nara, 632, japan phone: (07436) 5-1321 telex: labometa-b j63428 facsimile: (07436) 5-1532 warranty sharp warrants to customer that the products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. customer's exclusive remedy for breach of this warranty is that sharp will either (i) repair or replace, at its option, any product which fails during the warranty period because of such defect (if customer promptly reported the failure to sharp in writing) or, (ii) if sharp is unable to repair or replace, sharp will refund the purchase price of the product upon its return to sharp . this warranty does not apply to any product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than sharp . the warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. all express and implied warranties of merchantability, fitness for use and fitness for a particular purpose are specifically excluded. ? ?1997 by sharp corporation reference code smt96117 issued july 1996 LH28F040SUTD-Z4 4m (512k 8) flash memory

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